View AD7665ASTRL_1542851.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7665 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 16-bit, 570 ksps cmos adc functional block diagram dgnd dvdd avdd agnd ref refgnd switched cap dac cnvst impulse warp ognd 16 control logic and calibration circuitry clock ind(4r) 4r ovdd ad7665 ingnd pd reset byteswap ser/ par data[15:0] busy cs rd ob/ 2c serial port parallel interface ina(r) r inc(4r) 4r inb(2r) 2r features throughput: 570 ksps (warp mode) 500 ksps (normal mode) inl: 2.5 lsb max ( 0.0038% of full scale) 16-bit resolution with no missing codes s/(n+d): 90 db typ @ 180 khz thd: C100 db typ @ 180 khz analog input voltage ranges: bipolar: 10 v, 5 v, 2.5 v unipolar: 0 v to 10 v, 0 v to 5 v, 0 v to 2.5 v both ac and dc specifications no pipeline delay parallel (8/16 bits) and serial 5 v/3 v interface single 5 v supply operation power dissipation 64 mw typical 15 w @ 100 sps power-down mode: 7 w max package: 48-lead quad flatpack (lqfp) pin-to-pin compatible upgrade of the ad7664/ad7663 applications data acquisition communication instrumentation spectrum analysis medical instruments process control general description the ad7665 is a 16-bit, 570 ksps, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. it contains a high-speed 16-bit sampling adc, a resistor input scaler which allows various input ranges, an internal con- version clock, error correction circuits, and both serial and parallel system interface ports. the ad7665 is hardware factory-calibrated and is comprehen- sively tested to ensure such ac parameters as signal-to-noise ratio (snr) and total harmonic distortion (thd), in addition to the more traditional dc parameters of gain, offset, and linearity. it features a very high sampling rate mode (warp) and, for asynchronous conversion rate applications, a fast mode (nor- mal) and, for low power applications, a reduced power mode (impulse) where the power is scaled with the throughput. it is fabricated using analog devices high-performance, 0.6 micron cmos process and is available in a 48-lead lqfp with opera- tion specified from C40 c to +85 c. * patent pending. product highlights 1. fast throughput the ad7665 is a very high speed (570 ksps in warp mode and 500 ksps in normal mode), charge redistribution, 16-bit sar adc. 2. single supply operation the ad7665 operates from a single 5 v supply, dissipates only 64 mw typical, even lower when a reduced throughput is used with the reduced power mode (impulse) and a power- down mode. 3. superior inl the ad7665 has a maximum integral nonlinearity of 2.5 lsb with no missing 16-bit code. 4. serial or parallel interface versatile parallel (8 or 16 bits) or 2-wire serial interface arrangement compatible with both 3 v or 5 v logic.
rev. 0 C2C ad7665?pecifications parameter conditions min typ max unit resolution 16 bits analog input voltage range v ind C v ingnd 4 ref, 0 v to 4 ref, 2 ref (see table i) common-mode input voltage v ingnd C0.1 +0.5 v analog input cmrr f in = 180 khz 62 db input impedance see table i throughput speed complete cycle in warp mode 1.75 s throughput rate in warp mode 1 570 ksps time between conversions in warp mode 1 ms complete cycle in normal mode 2 s throughput rate in normal mode 0 500 ksps complete cycle in impulse mode 2.25 s throughput rate in impulse mode 0 444 ksps dc accuracy integral linearity error C2.5 +2.5 lsb 1 no missing codes 16 bits transition noise 0.7 lsb bipolar zero error 2 , t min to t max 5 v range, normal or C25 +25 lsb impulse modes other range or mode C0.06 +0.06 % of fsr bipolar full-scale error 2 , t min to t max C0.25 +0.25 % of fsr unipolar zero error 2 , t min to t max C0.18 +0.18 % of fsr unipolar full-scale error 2 , t min to t max C0.38 +0.38 % of fsr power supply sensitivity avdd = 5 v 5% 9.5 lsb ac accuracy signal-to-noise f in = 10 khz 89 90 db 3 f in = 180 khz 90 db spurious free dynamic range f in = 180 khz 100 db total harmonic distortion f in = 180 khz C100 db signal-to-(noise+distortion) f in = 10 khz 88.5 90 db f in = 180 khz, C60 db input 30 db C3 db input bandwidth 3.6 mhz sampling dynamics aperture delay 2ns aperture jitter 5 ps rms transient response full-scale step 1 s reference external reference voltage range 2.3 2.5 2.7 v external reference current drain 570 ksps throughput 114 a digital inputs logic levels v il C0.3 +0.8 v v ih +2.0 dvdd + 0.3 v i il C1 +1 a i ih C1 +1 a digital outputs data format parallel or serial 16-bit pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = C570 a ovdd C 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v operating current 4 570 ksps throughput avdd 14 ma dvdd 5 4.5 ma ovdd 5 20 a (?0 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.)
rev. 0 C3C ad7665 parameter conditions min typ max unit power supplies (continued) power dissipation 5, 6 444 ksps throughput 7 64 74 mw 100 sps throughput 7 15 w 570 ksps throughput 4 93 107 mw in power-down mode 8 7 w temperature range 9 specified performance t min to t max C40 +85 c notes 1 lsb means least significant bit. with the 5 v input range, one lsb is 152.588 v. 2 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full scale unless o therwise specified. 4 in warp mode. 5 tested in parallel reading mode. 6 tested with the 0 v to 5 v range and v in C v ingnd = 0 v. see power dissipation section. 7 in impulse mode. 8 with ovdd below dvdd + 0.3 v and all digital inputs forced to ovdd or ognd respect ively. 9 contact factory for extended temperature range. specifications subject to change without notice. table i. analog input configuration input voltage input range ind (4r) inc (4r) inb (2r) ina (r) impedance 1 4 ref v in ingnd ingnd ref 5.85 k ? 2 ref v in v in ingnd ref 3.41 k ? ref v in v in v in ref 2.56 k ? 0 v to 4 ref v in v in ingnd ingnd 3.41 k ? 0 v to 2 ref v in v in v in ingnd 2.56 k ? 0 v to ref v in v in v in v in note 2 notes 1 typical analog input impedance. 2 for this range the input is high impedance. timing specifications symbol min typ max unit refer to figures 11 and 12 convert pulsewidth t 1 5ns time between conversions t 2 1.75/2/2.25 note 1 s (warp mode/normal mode/impulse mode) cnvst low to busy high delay t 3 30 ns busy high all modes except in master serial read after t 4 0.75/1/1.25 s convert mode (warp mode/normal mode/impulse mode) aperture delay t 5 2ns end of conversion to busy low delay t 6 10 ns conversion time (warp mode/normal mode/impulse mode) t 7 0.75/1/1.25 s acquisition time t 8 1 s reset pulsewidth t 9 10 ns refer to figures 13, 14, and 15 (parallel interface modes) cnvst low to data valid delay t 10 0.75/1/1.25 s (warp mode/normal mode/impulse mode) data valid to busy low delay t 11 20 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 515ns refer to figures 17 and 18 (master serial interface modes) 2 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay (read during convert) t 17 25/275/525 ns (warp mode/normal mode/impulse mode) (?0 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.)
rev. 0 ad7665 C4C timing specifications (continued) symbol min typ max unit sync asserted to sclk first edge delay 3 t 18 4ns internal sclk period 3 t 19 25 40 ns internal sclk high 3 t 20 15 ns internal sclk low 3 t 21 9.5 ns sdout valid setup time 3 t 22 4.5 ns sdout valid hold time 3 t 23 2ns sclk last edge to sync delay 3 t 24 3 cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert 3 t 28 see table ii s cnvst low to sync asserted delay t 29 0.75/1/1.25 s master serial read after convert sync deasserted to busy low delay t 30 25 ns refer to figures 19 and 21 (slave serial interface modes) external sclk setup time t 31 5ns external sclk active edge to sdout delay t 32 316ns sdin setup time t 33 5ns sdin hold time t 34 5ns external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns notes 1 in warp mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time. 2 in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 3 in serial master read during convert mode. see table ii. specifications subject to change without notice. table ii. serial clock timings in master read after convert divsclk[1] 0011 divsclk[0] 0101 unit sync to sclk first edge delay minimum t 18 4 202020 ns internal sclk period minimum t 19 25 50 100 200 ns internal sclk period maximum t 19 40 70 140 280 ns internal sclk high minimum t 20 15 25 50 100 ns internal sclk low minimum t 21 9.5 24 49 99 ns sdout valid setup time minimum t 22 4.5 22 22 22 ns sdout valid hold time minimum t 23 243090 ns sclk last edge to sync delay minimum t 24 3 60 140 300 ns busy high width maximum (warp) t 28 1.5 2 3 5.25 s busy high width maximum (normal) t 28 1.75 2.25 3.25 5.5 s busy high width maximum (impulse) t 28 2 2.5 3.5 5.75 s
rev. 0 ad7665 C5C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7665 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf 1 note: 1 in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. figure 1. load circuit for digital interface timing, sdout, sync, sclk outputs, c l = 10 pf t delay t delay 0.8v 0.8v 0.8v 2v 2v 2v figure 2. voltage reference levels for timing pin configuration 48-lead lqfp (st-48) 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd nc byteswap ob/ 2c warp impulse nc = no connect ser/ par d0 d1 d2/divsclk[0] busy d15 d14 d13 ad7665 d3/divsclk[1] d12 d4/ext/ int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror nc nc nc nc nc ind(4r) inc(4r) inb(2r) ina(r) ingnd refgnd ref ordering guide model temperature range package description package option ad7665ast C40 c to +85 c quad flatpack (lqfp) st-48 AD7665ASTRL C40 c to +85 c quad flatpack (lqfp) st-48 eval-ad7665cb 1 evaluation board eval-control brd2 2 controller board notes 1 this board can be used as a stand-alone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstrat ion purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. absolute maximum ratings 1 analog inputs ind 2 , inc 2 , inb 2 . . . . . . . . . . . . . . . . . . . C11 v to +30 v ina, ref, ingnd, refgnd . . . . . . . . . . . . . . . . . . . . agnd C 0.3 v to avdd + 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . . . . . . . . . . 7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs . . . . . . . . . . . . . . . C0.3 v to dvdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . 700 mw junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91 c/w, jc = 30 c/w.
rev. 0 ad7665 C6C pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin. 2 avdd p input analog power pin. nominally 5 v. 3, 44C48 nc no connect. 4 byteswap parallel mode selection (8-/16-bit). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d[7:0]. 5ob/ 2c di straight binary/binary twos complement. when ob/ 2c is high, the digital output is straight binary; when low, the msb is inverted, resulting in a twos complement output from its internal shift register. 6 warp di mode selection. when high and impulse low, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. when low, full accuracy is maintained independent of the minimum conversion rate. 7 impulse di mode selection. when high and warp low, this input selects a reduced power mode. in this mode, the power dissipation is approximately proportional to the sampling rate. 8 ser/ par di serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. 9, 10 data[0:1] do bit 0 and bit 1 of the parallel port data output bus. when ser/ par is high, these outputs are in high impedance. 11, 12 data[2:3] or di/o when ser/ par is low, these outputs are used as bit 2 and bit 3 of the parallel port data output bus. divsclk[0:1] when ser/ par is high, ext/ int is low and rdc/sdin is low, which is the serial master read after convert mode. these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. in the other serial modes, these inputs are not used. 13 data[4] di/o when ser/ par is low, this output is used as bit 4 of the parallel port data output bus. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock, called respectively, master and slave mode. with ext/ int tied low, the internal clock is selected on sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input and the external clock is gated by cs . 14 data[5] di/o when ser/ par is low, this output is used as bit 5 of the parallel port data output bus. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. when low, sync is active high. when high, sync is active low. 15 data[6] di/o when ser/ par is low, this output is used as bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk sig- nal. it is active in both master and slave mode. 16 data[7] di/o when ser/ par is low, this output is used as bit 7 of the parallel port data output bus. or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an external data input or a read mode selection input, depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy chain the con- version results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the previous data is output on sdout during conversion. when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface (5 v or 3 v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground.
rev. 0 ad7665 C7C pin no. mnemonic type description 21 data[8] do when ser/ par is low, this output is used as bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in an on-chip register. the ad7665 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on sclk falling edge and valid on the next rising edge. 22 data[9] di/o when ser/ par is low, this output is used as bit 9 of the parallel port data output bus. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 data[10] do when ser/ par is low, this output is used as bit 10 of the parallel port data output bus. or sync when ser /par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and remains high while sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. 24 data[11] do when ser/ par is low, this output is used as bit 11 of the parallel port data output bus. or rderror when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25C28 data[12:15] do bit 12 to bit 15 of the parallel port data output bus. when ser/ par is high, these out- puts are in high impedance. 29 busy do busy output. transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external serial clock. 33 reset di reset input. when set to a logic high, reset the ad7665. current conversion, if any, is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high, power consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di start conversion. a falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. in impulse mode (impulse high and warp low), if cnvst is held low when the acquisition phase ( t 8 ) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 36 agnd p must be tied to analog ground. 37 ref ai reference input voltage. 38 refgnd ai reference input analog ground. 39 ingnd ai analog input ground. 40, 41, ina, inb, ai analog inputs. refer to table i for input range configuration. 42, 43 inc, ind notes ai = analog input. di = digital input. di/o = bidirectional digital. do = digital output. p = power.
rev. 0 ad7665 C8C definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 011 . . . 10 to 011 . . . 11 in twos complement coding) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (2.499886 v for the 2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. bipolar zero error the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. unipolar zero error in unipolar mode, the first transition should occur at a level 1/2 lsb above analog ground. the unipolar zero error is the deviation of the actual transition from that point. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following formula: enob = ( s /[ n + d ] db C 1.76)/6.02) and is expressed in bits. total harmonic distortion (thd) the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist fre- quency, excluding harmonics and dc. the value for snr is expressed in decibels. signal to (noise + distortion) ratio (s/[n+d]) the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyqu ist fre- quency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response the time required for the ad7665 to achieve its rated accuracy after a full-scale step function is applied to its input.
rev. 0 tpc 1. integral nonlinearity vs. code tpc 2. differential nonlinearity vs. code 70 60 50 40 30 20 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 number of units positive inl C lsb tpc 3. typical positive inl distribution (446 units) typical performance characteristics ad7665 C9C 80 70 60 50 40 30 20 10 0 C 3.0 C 2.7 C 2.7 C 2.1 C 1.8 C 1.5 C 1.2 C 0.9 C 0.6 C 0.3 number of units negative inl C lsb ,6+& , !!*7&&3/8 0019 932 7337 7204 870 22 0 0 0 1000 2000 3000 4000 5000 6000 7000 8000 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8005 code in hexa counts ,6+' )3%5&++ +, 001 214 3310 9468 3259 131 100 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 code in hexa counts tpc 6. histogram of 16,384 conversions of a dc input at the code center
rev. 0 ad7665 C10C C 0 C 20 C 40 C 60 C 80 C 100 C 120 C 140 C 160 C 180 0 57 114 171 228 285 amplitude C db of full scale frequency C khz 4096 point fft fs = 571khz f in = 45khz, C 0.5db snr = 90.1 db sinad = 89.7db thd = C 100.1db sfdr = 102.3db tpc 7. fft plot 100 95 90 85 80 75 70 1 10 100 1000 16.0 15.5 15.0 14.5 14.0 13.5 13.0 snr and s/[n +d] C db enob C bits frequency C khz snr sinad enob tpc 8. snr, s/(n+d), and enob vs. frequency 92 90 88 86 C 80 C 70 C 60 C 50 C 40 C 30 C 20 C 10 0 snr C (referred to full scale) C db input level C db tpc 9. snr vs. input level 96 93 90 87 84 C 98 C 100 C 102 C 104 C 55 C 35 C 15 5 25 45 65 85 105 125 snr C db thd C db temperature C c thd snr tpc 10. snr, thd vs. temperature thd 2nd harmonic 3rd harmonic sfdr C 60 C 65 C 70 C 75 C 80 C 85 C 90 C 95 C 100 C 105 C 110 C 115 110 105 100 95 90 85 80 75 70 65 60 1 10 100 1000 thd, harmonics C db sfdr C db frequency C khz tpc 11. thd, harmonics, and sfdr vs. frequency C 60 C 70 C 80 C 90 C 100 C 110 C 120 C 130 C 140 C 150 C 60 C 50 C 40 C 30 C 20 C 10 0 thd, harmonics C db input level C db thd 3rd harmonic 2nd harmonic tpc 12. thd, harmonics vs. input level
rev. 0 ad7665 C11C 50 40 30 20 10 0 0 50 100 150 200 t 12 delay C ns c l C pf tpc 13. typical delay vs. load capacitance c l 100000 10000 1000 100 10 1 0.1 0.01 0.001 1 10 100 1000 10000 100000 1000000 operating currents C a sampling rate C sps avdd, warp/normal dvdd, warp/normal avdd, impulse dvdd, impulse ovdd, all modes tpc 14. operating currents vs. sample rate 1000 900 800 700 600 500 400 300 200 100 0 C 55 C 35 C 15 5 25 45 65 85 105 power-down operating currents C na temperature C c dvdd av d d ovdd tpc 15. power-down operating currents vs. temperature
rev. 0 ad7665 C12C sw a comp sw b ind 4r ref refgnd lsb msb 32,768c ingnd 16,384c 4c 2c cc control logic switches control busy output code inc 4r ina r inb 2r cnvst 65,536c figure 3. adc simplified schematic circuit information the ad7665 is a fast, low-power, single-supply, precise 16-bit analog-to-digital converter (adc). the ad7665 features different modes to optimize performances according to the applications. in warp mode, the ad7665 is capable of converting 570,000 samples per second (570 ksps). the ad7665 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. it is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler. the ad7665 can be operated from a single 5 v supply and be interfa ced to either 5 v or 3 v digital logic. it is housed in a 48-lead lqfp package that combines space savings and flexible configurations as either serial or parallel interface. the ad7665 is a pin-to-pin-compatible upgrade of the ad7663 and ad7664. converter operation the ad7665 is a successive approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the input analog signal is, first, scaled down and level-shifted by the internal input resistive scaler which allows both unipolar ranges (0 v to 2.5 v, 0 v to 5 v, and 0 to 10 v) and bipolar ranges ( 2.5 v, 5 v, and 10 v). the output voltage range of the resistive scaler is always 0 v to 2.5 v. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparators negative input is connected to a dummy capaci- tor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparators positive input is connected to agnd via sw a . all independent switches are connected to the output of the resistive scaler. thus, the capacitor array is used as a sampling capacitor and acquires the analog signal. similarly, the dummy capacitor acquires the analog signal on ingnd input. when the acquisition phase is complete, and the cnvst input goes or is low, a conversion phase is initiated. when the conversion phase begins, sw a and sw b are opened first. the capacitor array and the dummy capacitor are then disconnected from the inputs and connected to the refgnd input. therefore, the differen- tial voltage between the output of the resistive scaler and ingnd captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd or ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4...v ref /65536). the control logic toggles these switches, starting with the msb first, in order to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings busy output low. modes of operation the ad7665 features three modes of operations, warp, normal, and impulse. each of these modes is more suitable for specific applications. the warp mode allows the fastest conversion rate up to 570 ksps. however, in this mode, and this mode only, the full specified accu- racy is guaranteed only when the time between conversion does not exceed 1 ms. if the time between two consecutive conver sions is longer than 1 ms, for instance, after power-up, the first con ver- sion result should be ignored. this mode makes the ad7665 ideal for applications where both high accuracy and fast sample rate are required. the normal mode is the fastest mode (500 ksps) without any limitation about the time between conversions. this mode m akes the ad7665 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. the maximum throughput in this mode is 444 ksps. when operating at 100 sps, for ex- ample, it typically consumes only 15 w. this feature makes the ad7665 ideal for battery-powered applications. transfer functions using the ob/ 2c digital input, the ad7665 offers two output codings: straight binary and twos complement. the ideal tr ansfer characteristic for the ad7665 is shown in figure 4 and table iii. 000...000 000...001 000...010 111...101 111...110 111...111 adc code - straight binary analog input +fs C 1.5 lsb +fs C 1 lsb C fs + 1 lsb C fs C fs + 0.5 lsb figure 4. adc ideal transfer function
rev. 0 ad7665 C13C table iii. output codes and ideal input voltages digital output code (hexa) straight two? description analog input binary complement full-scale range 10 v 5 v 2.5 v 0 v to 10 v 0 v to 5 v 0 v to 2.5 v least significant bit 305.2 v 152.6 v 76.3 v 152.6 v 76.3 v 38.15 v fsr C 1 lsb 9.999695 v 4.999847 v 2.499924 v 9.999847 v 4.999924 v 2.499962 v ffff 1 7fff 1 midscale + 1 lsb 305.2 v 152.6 v 76.3 v 5.000153 v 2.570076 v 1.257038 v 8001 0001 midscale 0 v 0 v 0 v 5 v 2.5 v 1.25 v 8000 0000 midscale C 1 lsb C305.2 v C152.6 v C76.3 v 4.999847 v 2.499924 v 1.249962 v 7fff ffff Cfsr + 1 lsb C9.999695 v C4.999847 v C2.499924 v 152.6 v 76.3 v 38.15 v 0001 8001 Cfsr C10 v C5 v C2.5 v 0 v 0 v 0 v 0000 2 8000 2 notes 1 this is also the code for an overrange analog input. 2 this is also the code for an underrange analog input. 100nf 10 f 100nf 10 f avdd 10 f 100nf agnd dgnd dvdd ovdd ognd ser/ par cnvst busy sdout sclk rd cs reset pd refgnd c ref 2.5v ref ref 100 d clock ad7665 c/ p/dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd ob/ 2c note 8 byteswap dvdd 50k 100nf 1m ina 100nf u2 ind ingnd analog input ( 10v) c c 2.7nf u1 15 10 f note 2 note 1 note 3 note 7 note 4 50 inc inb note 6 notes : 1. see voltage reference input chapter. 2. with the recommended voltage references, c ref is 47 f. see section voltage reference input section. 3. optional circuitry for hardware gain calibration. 4. for bipolar range only. see scaler reference input section. 5. the ad8021 is recommended. see driver amplifier choice section. 6. with 0 to 2.5v range only. see analog inputs section. 7. option. see power supply section. 8. optional low jitter cnvst . see conversion control section. + + + ++ + + ad8031 ad8021 50 adr421 note 5 warp impulse figure 5. typical connection diagram ( 10 v range shown)
rev. 0 ad7665 C14C typical connection diagram figure 5 shows a typical connection diagram for the ad7665. different circuitry shown on this diagram is optional and is discussed below. analog inputs the ad7665 is specified to operate with six full-scale analog input ranges. connections required for each of the four ana- log inputs, ind, inc, inb, ina, and the resulting full-scale ranges, are shown in table i. the typical input impedance for each analog input range is also shown. figure 6 shows a simplified analog input section of the ad7665. the four resistors connected to the four analog inputs form a resistive scaler which scales-down and shifts the analog input range to a common input range of 0 v to 2.5 v at the input of the switched capacitive adc. inc inb ina 4r 2r r ind 4r agnd avdd r1 c s r = 1.28k figure 6. simplified analog input by connecting the four inputs ina, inb, inc, ind to the input signal itself, the ground, or a 2.5 v reference, other analog input ranges can be obtained. the diodes shown in figure 6 provide esd protection for the four analog inputs. the inputs inb, inc, ind, have a high voltage protection (C11 v to +30 v) to allow wide input voltage range. care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs including ina (0 v to 5 v). this will cause these diodes to become forward- biased and start conducting current. these diodes can handle a forward-biased current of 120 ma maximum. for instance, when using the 0 v to 2.5 v input range, these conditions could eventu- ally occur on the input ina when the input buffers (u1) supplies are different from avdd. in such case, an input buffer with a short-circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differen- tial signal between the output of the resistive scaler and ingnd. unlike o ther converters, the ingnd input is sampled at the same time as the inputs. by using this differential input, small signals common to both inputs are reje cted as shown in figure 7, which represents the typical cmrr over frequency. for in stance, by using ingnd to sense a remote signal ground, difference of ground potentials between the sensor and the local adc ground are eliminated. 75 70 65 60 55 50 45 40 35 1 10 100 1000 10000 cmrr C db frequency C khz figure 7. analog input cmrr vs. frequency during the acquisition phase for ac signals, the ad7665 behaves like a one-pole rc filter consisting of the equivalent resistance of the resistive scaler r/2 in series with r1 and c s . the resistor r1 is typically 100 ? and is a lumped component made up of some serial resistor and the on-resistance of the switches. the capacitor c s is typically 60 pf and is mainly the adc sampling capacitor. this one-pole filter with a typical C3 db cutoff frequency of 3.6 mhz reduces undesirable aliasing effects and limits the noise coming from the inputs. except when using the 0 v to 2.5 v analog input voltage range, the ad7665 has to be driven by a very low impedance source to avoid gain errors. that can be done by using a driver amplifier whose choice is eased by the primarily resistive analog input circuitry of the ad7665. when using the 0 v to 2.5 v analog input voltage range, the input impedance of the ad7665 is very high so the ad7665 can be driven directly by a low impedance source without gain e rror. that allows, as shown in figure 5, putting an external one- pole rc filter between the output of the amplifier output and the adc analog inputs to even further improve the noise filtering done by the ad7665 analog input circuit. however, the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion (thd). the maximum source impedance depends on the amount of total thd that can be tolerated. the thd degradation is a function of the source impedance and the maximum input frequency as shown in figure 8.
rev. 0 ad7665 C15C frequency C khz C 110 0 100 thd C 100 C 90 C 80 C 70 1000 r = 50 r = 11 r = 100 figure 8. thd vs. analog input frequency and input resistance (0 v to 2.5 v only) driver amplifier choice although the ad7665 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? the driver amplifier and the ad7665 analog input circuit must be able, together, to settle for a full-scale step the capaci- tor array at a 16-bit level (0.0015%). in the amplifiers data sheet, the settling at 0.1% to 0.01% is more commonly speci- fied. it could significantly differ from the settling time at 16-bit level and it should therefore be verified prior to the driver selection. the tiny op amp ad8021, which combines ultralow noise and a high-gain bandwidth, meets this settling time requirement even when used with a high gain up to 13. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transi- tion noise performance of the ad7665. the noise coming from the driver is first scaled down by the resistive scaler according to the analog input voltage range used, and is then filtered by the ad7665 analog input circuit one-pole, low- pass filter made by (r/2 + r1) and c s . the snr degrada tion due to the amplifier is: snr f ne fsr loss db n = + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 20 28 784 2 25 1000 3 2 log . C where f C3 db is the C3 db input bandwidth of the ad7665 (3.6 mhz) or the cut-off frequ ency of the input filter if any used (0 v to 2.5 v range). n is the noise factor of the amplifier (1 if in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/(hz) 1/2 . fsr is the full-scale span (i.e., 5 v for 2.5 v range). for instance, when using the 0 v to 2.5 v range, a driver like the ad8021, with an equivalent input noise of 2 nv/ hz and configured as a buffer, thus with a noise gain of 1, the snr degrades by only 0.12 db. ? the driver needs to have a thd performance suitable to that of the ad7665. tpc 8 gives the thd versus frequency that the driver should preferably exceed. the ad8021 meets these requirements and is usually appropri- ate for almost all applications. the ad8021 needs an external compensation capacitor of 10 pf. this capacitor should have good linearity as an npo ceramic or mica type. the ad8022 could also be used where dual version is needed and gain of 1 is used. the ad829 is another alternative where high-frequency (above 100 khz) performance is not required. in gain of 1, it requires an 82 pf compensation capacitor. the ad8610 is another option where low bias current is needed in low frequency applications. voltage reference input the ad7665 uses an external 2.5 v voltage reference. the voltage reference input ref of the ad7665 has a dynamic input impedance. therefore, it should be driven by a low impedance source with an efficient decoupling between ref and refgnd inputs. this decoupling depends on the choice of the voltage reference, but usually consists of a low esr tanta- lum capacitor connected to the ref and refgnd inputs with minimum parasitic inductance. 47 f is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: C the low-noise, low-temperature drift adr421 and ad780 voltage references. C the low-power adr291 voltage reference. C the low-cost ad1582 voltage reference. for applications using multiple ad7665s, it is more effective to buffer the reference voltage with a low-noise, very stable op amp such as the ad8031. care should also be taken with the reference temperature coeffi- cient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/ c tempco of the reference changes the full scale by 1 lsb/ c. scaler reference input (bipolar input ranges) when using the ad7665 with bipolar input ranges, the connec- tion diagram in figure 5 shows a reference buffer amplifier. this buffer amplifier is required to isolate the refin pin from the signal dependent current in the ain pin. a high-speed op amp such as the ad8031 can be used with a single 5 v power supply without degrading the performance of the ad7665. the buffer must have good settling characteristics and provide low total noise within the input bandwidth of the ad7665. power supply the ad7665 uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and 5.25 v. to reduce the number of supplies needed, the digital core ( dvdd) can be supplied through a simple rc filter from the analog supply as shown in figure 5. the ad7665 is inde- pendent of power supply sequencing and thus free from supply voltage induced latchup. additionally, it is very insensitive to power supply variations over a wide frequency range as shown in figure 9.
rev. 0 ad7665 C16C 75 70 65 60 55 50 45 40 35 1 10 100 1000 psrr C db frequency C khz figure 9. psrr vs. frequency power dissipation in impulse mode, the ad7665 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows a significant power saving when the conversion rate is reduced as shown in figure 10. this feature makes the ad7665 ideal for very low-power battery applications. this does not take into account the power, if any, dissipated by the input resistive scaler which depends on the input voltage range used and the analog input voltage even in power-down mode. there is no power dissipated when the 0 v to 2.5 v is used or when both the analog input voltage is 0 v and a unipolar range, 0 to 5 v or 0 to 10 v, is used. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., dvdd and dgnd) and ovdd should not exceed dvdd by more than 0.3 v. 100000 10000 1000 100 10 1 0.1 1 10 100 1000 10000 100000 1000000 power dissipation C w sampling rate C sps warp/normal impulse figure 10. power dissipation vs. sample rate conversion control figure 11 shows the detailed timing diagrams of the conversion process. the ad7665 is controlled by the signal cnvst which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conver- sion is complete. the cnvst signal operates independently of cs and rd signals. cnvst busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acquire convert acquire convert figure 11. basic conversion timing in impulse mode, conversions can be automatically initiated. if cnvst is held low when busy is low, the ad7665 controls the acquisition phase and then automatically initiates a new conversion. by keeping cnvst low, the ad7665 keeps the conversion process running by itself. it should be noted that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the ad7665 could sometimes run slightly faster then the guaranteed limits in the impulse mode of 444 ksps. this feature does not exist in warp or nor- mal modes. although cnvst is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. it is a good thing to shield the cnvst trace with ground and also to add a low value serial resistor (i.e., 50 v) termination close to the output of the com- ponent which drives this line. for applications where the snr is critical, cnvst signal should have a very low jitter. some solutions to achieve that is to use a dedicated oscillator for cnvst generation, or at least to clock it with a high-frequency low-jitter clock as shown in figure 5. t 9 t 8 reset data busy cnvst figure 12. reset timing
rev. 0 ad7665 C17C digital interface the ad7665 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7665 digital interface also accommodates both 3 v or 5 v logic by simply connecting the ovdd supply pin of the ad7665 to the host system interface digital supply. finally, by using the ob/ 2c input pin, both twos complement or straight binary coding can be used. the two signals cs and rd control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7665 in multicircuits applications and is held low in a single ad7665 design. rd is generally used to enable the conversion result on the data bus. t 1 t 3 t 4 t 11 cnvst busy data bus cs = rd = 0 t 10 previous conversion data new data figure 13. master parallel data timing for reading (continuous read) parallel interface the ad7665 is configured to use the parallel interface when the ser/ par is held low. the data can be read either after each conversion, which is during the next acquisition phase, or dur- ing the following conversion as shown, respectively, in figure 14 and fi gure 15. when the data is read during the conversion, however, it is recommended that it be read only during the first half of the conversion phase. that avoids any potential feed- through between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion busy data bus cs rd t 12 t 13 figure 14. slave parallel data timing for reading (read after convert) previous conversion t 1 t 3 t 12 t 13 t 4 cs = 0 cnvst , rd busy data bus figure 15. slave parallel data timing for reading (read during convert) the byteswap pin allows a glueless interface to an 8-bit bus. as shown in figure 16, the lsb byte is output on d[7:0] and the msb is output on d[15:8] when byteswap is low. when byteswap is high, the lsb and msb bytes are swapped and the lsb is output on d[15:8] and the msb is output on d[7:0]. by connecting byteswap to an address line, the 16 data bits can be read in 2 bytes on either d[15:8] or d[7:0]. cs byte pins d[15:8] hi-z high byte low byte hi-z hi-z high byte low byte hi-z t 12 t 12 t 13 pins d[7:0] rd figure 16. 8-bit parallel interface serial interface the ad7665 is configured to use the serial interface when the ser/ par is held high. the ad7665 outputs 16 bits of data, msb first, on the sdout pin. this data is synchronized with the 16 clock pulses provided on sclk pin. the output data is valid on both the rising and falling edge of the data clock. master serial interface internal clock the ad7665 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. it also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. depending on rdc/sdin input, the data can be read after each conversion or during conversion. figure 17 and figure 18 show the detailed timing diagrams of these two modes. usually, because the ad7665 is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used.
rev. 0 ad7665 C18C t 3 busy cs , rd cnvst sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 123 141516 d15 d14 d2 d1 d0 x ext/ int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 figure 17. master serial data timing for reading (read after convert) ext/ int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 141516 t 18 busy sync sclk sdout cs , rd cnvst figure 18. master serial data timing for reading (read previous conversion during convert)
rev. 0 ad7665 C19C cs sclk sdout d15 d14 d1 d0 d13 x15 x14 x13 x1 x0 y15 y14 busy sdin invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 t 34 x15 x14 x 123 1415161718 ext/ int = 1 rd = 0 figure 19. slave serial data timing for reading (read after convert) in read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimizes potential feedthrough between digital activity and the critical conversion decisions. in read-after-conversion mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer busy width. slave serial interface external clock the ad7665 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs and the data are output when both cs and rd are low. thus, depending on cs , the data can be read after each conversion or during the follow- ing conversion. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either nor- mally high or normally low when inactive. figure 19 and figure 21 show the detailed timing diagrams of these methods. while the ad7665 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. this is par- ticularly important during the second half of the conversion phase because the ad7665 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recom- mended that when an external clock is being provided, it is a discontinuous clock that is toggling only when busy is low or, more importantly, that is does not transition during the latter half of busy high. external discontinuous clock data read after conversion though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 19 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the result of this conversion can be read while both cs and rd are low. the data is shifted out, msb first, with 16 clock pulses and is valid on both rising and falling edge of the clock. among the advantages of this method, the conversion perfor- mance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is to be able to read the data at any speed up to 40 mhz which accommodates both slow digital host interface and the fastest serial reading. finally, in this mode only, the ad7665 provides a daisy chain feature using the rdc/sdin input pin for cascading multiple converters together. this feature is useful for reducing compo- nent count and wiring connections when desired as, for instance, in isolated multiconverter applications. an example of the concatenation of two devices is shown in fig- ure 20. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the opposite edge of sclk of the one used to shift out the data on sdout. hence, the msb of the upstream con- verter just follows the lsb of the downstream converter on the next sclk cycle. cnvst cs sclk sdout rdc/sdin busy busy data out ad7665 #1 (downstream) busy out cnvst cs sclk ad7665 #2 (upstream) rdc/sdin sdout sclk in cs in cnvst in figure 20. two ad7665s in a daisy-chain configuration
rev. 0 ad7665 C20C cnvst sdout sclk d1 d0 x d15 d14 d13 12 3 141516 t 3 t 35 t 36 t 37 t 31 t 32 t 16 busy invsclk = 0 cs , rd ext/ int = 1 rd = 0 figure 21. slave serial data timing for reading (read previous conversion during convert) external clock data read during conversion figure 21 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out, msb first, with 16 clock pulses and is valid on both rising and falling edge of the clock. the 16 bits have to be read before the current conversion is complete. if that is not done, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy chain fea- ture in this mode and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock of, at least 25 mhz, when impulse mode is used, 40 mhz when normal or warp mode is used, is recom- mended to ensure that all the bits are read during the first half of the conversion phase. it is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. that allows the use of a slower clock speed like 10 mhz in impulse m ode, 12 mhz in normal mode and 15 mhz in warp mode. microprocessor interfacing the ad7665 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal process- ing applications interfacing to a digital signal processor. the ad7665 is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7665 to prevent digital noise from coupling into the adc. the following sections illustrate the use of the ad7665 with an spi equipped microcontroller, the adsp- 21065l and adsp-218x signal processors. spi interface (mc68hc11) figure 22 shows an interface diagram between the ad7665 and an spi-equipped microcontroller like the mc68hc11. to accommodate the slower speed of the microcontroller, the ad7665 acts as a slave device and data must be read after con- version. this mode also allows the daisy chain feature. the convert command could be initiated in response to an internal timer interrupt. the reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conver- sion signal (busy going low) using an interrupt line of the microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1 and spi interrupt enable (spie) = 1 by writing to the spi control regis- ter (spcr). the irq is configured for edge-sensitive-only operation (irqe = 1 in option register). irq mc68hc11 * cnvst ad7665 * busy cs miso/sdi sck i/o port sdout sclk invsclk ext/ int dvdd * additional pins omitted for clarity ser/ par rd figure 22. interfacing the ad7665 to spi interface adsp-21065l in master serial interface as shown in figure 23, the ad7665 can be interfaced to the adsp-21065l using the serial interface in master mode without any glue logic required. this mode combines the advantages of reducing the wire connections and the ability to read the data during or after conversion maximum speed transfer (divsclk[0:1] both low). the ad7665 is configured for the internal clock mode (ext/ int low) and acts, therefore, as the master device. the convert command can be generated by either an external low jitter oscil- lator or, as shown, by a flag output of the adsp-21065l or by a frame output tfs of one serial port of the adsp-21065l which can be used like a timer. the serial port on the adsp- 21065l is configured for external clock (irfs = 0), rising edge active (ckre = 1), external late framed sync signals (irfs = 0, lafs = 1, rfsr = 1) and active high (lrfs = 0). the serial port of the adsp-21065l is configured by writing to its receive control register (srctl)see adsp-2106x sharc user? manual . because the serial port within the adsp-21065l will
rev. 0 ad7665 C21C be seeing a discontinuous clock, an initial word reading has to be done after the adsp-21065l has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. rfs adsp-21065l * sharc cnvst ad7665 * cs sync rd dr rclk flag or tfs sdout sclk invsync invsclk ext/ int rdc/sdin ser/ par dvdd * additional pins omitted for clarity figure 23. interfacing to the adsp-21065l using the serial master mode application hints layout the ad7665 has very good immunity to noise on the power supplies as can be seen in figure 9. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7665 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7665, or, at least, as close as possible to the ad7665. if the ad7665 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the ad7665. it is recommended to avoid running digital lines under the de- vice as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7665 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the ad7665 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplies impedance presented to the ad7665 and reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supplies pins avdd, dvdd and ovdd close to, and ideally right up against these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located in the vicinity of the adc to further reduce low fre- quency ripple. the dvdd supply of the ad7665 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, it is recom- mended if no separate supply available, to connect the dvdd digital supply to the analog supply avdd through an rc filter as shown in figure 5, and connect the system supply to the interface digital supply ovdd and the remaining digital cir- cuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. the ad7665 has five different ground pins; ingnd, refgnd, agnd, dgnd, and ognd. ingnd is used to sense the analog input signal. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. this ground must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is impor- tant. the decoupling capacitor should be close to the adc and connected with short and large traces to minimize parasitic inductances. evaluating the ad7665 performance a recommended layout for the ad7665 is outlined in the evalu- ation board for the ad7665. the evaluation board package includes a fully assembled and tested evaluation board, docu- mentation, and software for controlling the board from a pc via the eval-control board.
rev. 0 ad7665 C22C 48-lead quad flatpack (lqfp) (st-48) 0.039 (1.00) ref top view (pins down) 1 12 13 25 24 36 37 48 0.280 (7.1) 0.276 (7.0) sq 0.272 (6.9) 0.362 (9.19) 0.354 (9.00) sq 0.346 (8.79) 0.010 (0.26) 0.007 (0.18) 0.006 (0.15) 0.023 (0.58) 0.020 (0.50) 0.017 (0.42) seating plane 0 min 0.007 (0.177) 0.005 (0.127) 0.004 (0.107) 0.006 (0.15) 0.004 (0.10) 0.002 (0.05) 0.028 (0.7) 0.020 (0.5) 0.012 (0.3) 0.067 (1.70) 0.059 (1.50) 0.055 (1.40) 7 3.5 0 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) outline dimensions dimensions shown in inches and (mm).
C23C
C24C c01846C2.5C4/01(0) printed in u.s.a.

▲Up To Search▲

Price & Availability of AD7665ASTRL

	To Download AD7665ASTRL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .